1. Field of the Invention
The present invention relates generally to interconnection structures of semiconductor integrated circuit devices and a manufacturing method thereof and, more particularly, to an interconnection structure of a semiconductor integrated circuit device in which multi layer aluminum interconnection layers are mutually connected through a connection hole, and to a manufacture method thereof.
2. Description of the Background Art
In general, a semiconductor device comprises a semiconductor substrate and elements such as transistors formed thereon. Various interconnection layers are formed on the semiconductor substrate for electrically connecting these elements to each other and to an external circuit. These interconnection layers have been formed of polysilicon films, refractory metal films, refractory metal silicide films, aluminum films and aluminum alloy films. In recent years, reduction of the interconnection layer resistance has been required in the semiconductor integrated circuit devices which are highly integrated for high speed operations. Therefore, the semiconductor integrated circuit devices essentially require aluminum multilayer interconnection structure formed of aluminum films or aluminum alloy films having a small specific resistance. An example of the conventional aluminum multilayer interconnection structure is disclosed in "High Performance Multilevel Interconnection System with Stacked Interlayer Dielectrics by Plasma CVD and Bias Sputtering", M. Abe et al. pp. 404-410, VMIC Conference, Jun. 12-13, 1989.
FIG. 17 is a partial sectional view showing an example of an aluminum multilayer interconnection structure in the conventional semiconductor integrated circuit device. In the figure, a silicon semiconductor substrate 1 bears DRAM (Dynamic Random Access Memory) cells 2 which are formed in a stacked cell structure. A base insulating film 3 is formed on DRAM cells 2. First aluminum interconnection layers 4 are formed on the base insulating film 3 with predetermined spaces between each other. The first aluminum interconnections 4 are covered with an interlayer insulating film 5, which is provided with connection holes 6 (also called a "via-hole" or "through-hole"). Second aluminum interconnection layers 7 are formed on the interlayer insulating film 5 and are connected to the first aluminum interconnection layers 4 through the connection holes 6. A protection insulating film 8 is formed to cover DRAM cells 2, first aluminum interconnection layers 4 and second aluminum interconnection layers 7 to protect them against moisture and other external material.
In the conventional aluminum multilayer interconnection structure shown in FIG. 17, yield and reliability of the semiconductor device technically depends on stability of a connection part (hereinafter called "via-hole portion") between the first aluminum interconnection layer and the second aluminum interconnection layer. A manufacturing method of the conventional aluminum multilayer interconnection structure shown in FIG. 17 will be described particularly with respect to formation of the via-hole part. The multilayer interconnection structure has been generally formed of a combination of polysilicon interconnections, refractory metal interconnections, refractory metal silicide interconnection layers and aluminum interconnections. However, a description will be made hereinafter of an aluminum two-layer structure in which both interconnection layers in the first and the second layers are aluminum interconnection layers.
FIGS. 18 through 24 are partial sectional views showing a manufacturing method of the aluminum two-layer interconnection structure in the conventional semiconductor integrated circuit device in the order of the manufacturing steps.
Referring to FIG. 18, DRAM cell 2 is formed on the surface of silicon semiconductor substrate 1. DRAM cell 2 is formed of an element separator oxide film 301, a transfer gate electrode 302, an impurity diffusion layer 303, a word line 304, a memory node 305, a capacitor insulating film 306, a cell plate 307 and an insulating film 309.
Referring to FIG. 19, base insulating film 3 is formed on the whole surface of silicon semiconductor substrate 1 in which DRAM cell 2 is formed. Then, photolithography and etching technique are used for forming a contact hole 308 at a predetermined position in the base insulating film. First aluminum interconnection layer 4 is formed as a bit line and electrically contacts with the impurity diffusion layer 303 through this contact hole 308. Recently, a semiconductor integrated circuit device in which sizes of elements are reduced to an order of submicron has employed the interconnection layer as first aluminum interconnection layer 4, in which a barrier metal film 310 such as titanium nitride (TiN) or titanium-tungsten (TiW) and an aluminum alloy film 311 of Al-Si-Cu or the like are combined. The aluminum interconnection layer having such structure has been used for the following reasons.
(i) If the aluminum is in direct contact with the silicon substrate (impurity diffusion layer) at the contact portion, an abnormal reaction (alloy spike) is locally caused. This produces a reaction layer which breaks through a region of the impurity diffusion layer and extends downwardly in the silicon substrate resulting in a junction leak in the impurity diffusion layer. In order to prevent this, the barrier metal film is formed in direct contact with the silicon substrate (impurity diffusion layer).
(ii) Silicon in the aluminum alloy film is deposited at the contact portion due to the solid-phase epitaxial growth which causes imperfect contact. In order to prevent this, the barrier metal film is formed under the aluminum alloy film.
(iii) An interlayer insulating film and protection insulating film are formed on the aluminum interconnection layer. A film stress by these upper insulating films may break the aluminum interconnection layers. In order to increase the resistance against such stress migration phenomenon, the barrier metal film is formed under the aluminum alloy film.
A film forming first aluminum interconnection layer 4 is usually formed by deposition in a sputtering method and subsequent patterning thereof using the photolithography and etching technology.
Referring to FIG. 20, interlayer insulating film 5 is formed on the whole surface of the first aluminum interconnection layer 4. Interlayer insulating film 5 is formed of a combination of a silicon oxide film 321 formed by, for example, the CVD (Chemical Vapor Deposition), an inorganic application insulating film 322 and a silicon oxide film 323 formed by the CVD.
Silicon oxide film 321 is formed by the CVD utilizing heat and plasma at formation temperatures of 300.degree.-450.degree. C., using a mixture of a silane (SiH.sub.4) gas and an oxygen (O.sub.2) gas or a nitrous oxide (N.sub.2 O) gas. Recently, a silicon oxide film has been formed from an organic silane contained material such as TEOS (Tetra-Ethyl-Ortho-Silicate) characterized by a good step coverage.
Inorganic application insulating film 322 formed for flattening generally includes silanol (Si (OH).sub.4) or the like as the main component. After rotary application of material including silanol or the like as the main component, baking is carried out at temperatures of 400.degree.-450.degree. C. for changing the material to a silicon oxide film, whereby the surface of the silicon oxide film 321 formed by the CVD is flattened. Since inorganic application insulating film 322 has a high hygroscopic property, it may cause a disadvantage such as gas emission if the insulator film 322 is exposed at a sidewall of the via-hole portion. Therefore, inorganic application insulating film 322 is subjected to an etch back processing by dry etching using a fluorine contained gas or an argon gas so that the surface of inorganic application insulating film 322 is not exposed at the sidewall of the via-hole portion.
A silicon oxide film 323 is formed on the inorganic application insulating film 322 in the manner similar to that for forming silicon oxide film 321.
Referring to FIG. 21, connection hole 6 is formed by photolithography and etching to expose a predetermined surface of the first aluminum interconnection layer 4. The step is carried out as follows.
A photoresist 324 is provided to cover an region except for where connection hole 6 is formed by photolithography. Then, interlayer insulating film 5 is selectively removed to open connection hole 6.
Photoresist 324 as well as a reaction product and the like produced in the etching are removed by an oxygen (O.sub.2) plasma and a wet chemical processing after the etching.
Referring to FIG. 22, in the step for forming connection hole 6, the surface of the first aluminum interconnection layer 4 is exposed to plasma of a fluorine contained gas such as CHF.sub.3 or an oxygen gas, so that a deterioration layer 201 (a layer including fluoride and oxide) of aluminum is formed in a thickness of about 100 .ANG. on the surface of first aluminum interconnection layer 4 in connection hole 6. Therefore, in order to remove an insulating film of the thin deterioration layer of aluminum so as to obtain a stable contact resistance, sputter etching using argon ions (Ar.sup.+) 202 is carried out prior to the formation of the second aluminum interconnection layer.
Then, as shown in FIG. 23, the second aluminum interconnection layer 7 is continuously deposited in a vacuum using the sputter method. For second aluminum interconnection layer 7, a film of aluminum alloy such as Al-Si, Al-Si-Cu, or Al-Cu is used. These films are formed by the patterning using the photolithography and etching in the manner similar to that of the first aluminum interconnection layer.
After second aluminum interconnection layer 7 is formed, heat treatment is carried out at temperatures of about 400.degree.-450.degree. C. so that first and second aluminum interconnection layers 4 and 7 contact with each other in connection hole 6.
Finally, as shown in FIG. 24, protection insulating film 8 such as a silicon oxide film or a silicon nitride film is deposited on second aluminum interconnection layer 7 by the CVD so as to protect semiconductor elements and interconnections against moisture or the like entering from the external.
The conventional aluminum multilayer interconnection structure has the following problems.
Due to the miniaturization of interconnections, a diameter of connection hole 6 has been reduced. If the diameter of connection hole 6 is at a sub-micron level, a problem may arise relating to stability and reliability in the electrical connection at connection hole 6. In the conventional case, as described above, the sputter etching is carried out using argon ions prior to the formation of second aluminum interconnection layer 7. In this etching as shown in FIG. 25 A, argon ions 202 remove a deterioration layer 201 (a layer including fluoride and oxide) formed on the surface of first aluminum interconnection layer 4 in connection hole 6. In the conventional structure in which connection hole 6 has a relatively small aspect ratio (B/A) [A: a diameter of the connection hole, B: a film thickness (about 1 .mu.m) of the interlayer insulating film] of not more than 1, particles 203 of oxide and fluoride of aluminum sputtered with argon ions 202 sufficiently scatter up to the outside of connection hole 6, as shown in FIG. 25A. Therefore, by removing deterioration layer 201 of aluminum, the surface of the first aluminum interconnection layer 4 in connection hole 6 can be cleaned.
However, if connection hole 6 having the diameter at the sub-micron level on the aspect ratio (B/A) over 1, as shown in FIG. 25B, the particles 203 of the oxide and fluoride of aluminum sputtered by argon ions 202 is partially blocked by the sidewall of connection hole 6, and thus can not scatter to the side of connection hole 6. Therefore, some of the particles 204 re-stick onto the inside of connection hole 6. This phenomenon is reported in "A New Reliability Problem Associated with Ar Ion Sputter Cleaning of Interconnect Vias", H. Tomioka et al., IEEE/IRPS, 1989, pp. 53-58.
As a result, even if the continuous deposition of second aluminum interconnection layer 7 in a vacuum is carried out as a next step, the particles 204 of the oxide and fluoride of aluminum, which have stuck onto an interface 205 between first and second aluminum interconnection layers 4 and 7 in connection hole 6 during the sputtering etching, remain there, as shown in FIG. 26A. Thereby, in the heat treatment at about 400.degree.-450.degree. C. after the formation of the second aluminum interconnection layer, mixing can not be sufficiently carried out at the interface 205 between the first and second aluminum interconnection layers.
Consequently, a contact resistance (called "via-hole resistance") in connection hole 6 may be increased and/or an open failure (a failure in conduction between the first and second aluminum interconnection layers) may be caused.
Further, even if the initial via-hole resistance has a correct value owing to a heat treatment at 400.degree.-450.degree. C. described above, the mixing has not been sufficiently carried out at interface 205 between the first and second aluminum interconnection layers. Therefore, the reliability in connection hole 6 such as resistance against the electro-migration and stress-migration is reduced.
For an approach to alleviate such problems, as shown in FIG. 26B, a first aluminum interconnection layer 4 has been recently used in which a film of refractory metal such as tungsten (W) and titanium-tungsten (Ti-W), a film of refractory metal compound such as titanium nitride (TiN), a film of refractory metal silicide such as molybdenum-silicide (MoSi.sub.2) and tungsten-silicide (WSi.sub.2), or a film containing refractory elements such as an amorphous-silicon film are provided on a surface of an aluminum alloy film 311 of a first layer. In such structures, it is known that refractory element-containing film 312 produces thinner deterioration layer in the step of the formation of the through-hole compared to aluminum alloy film 311.
However, even when the above described structure is adopted, the re-sticking phenomenon in the connection hole at a sub-micron level in sputter-etching is not completely prevented. Since a thinner deterioration layer is produced on the surface of a refractory element-containing film 312 which is the uppermost layer of first aluminum interconnection layer 4, a small amount of sputter-etching is sufficient, and therefore the re-sticking is reduced to some degree.
Therefore, when second aluminum interconnection layer 7 is formed on the refractory element-containing film particles 314 of the fluoride and oxide of tungsten which re-stuck at the time of sputter-etching exist on an interface 205 of first aluminum interconnection layer 4 and second aluminum interconnection layer 7, as shown in FIG. 26C. This prevents mixing in interface 205 of the first aluminum interconnection layer and the second aluminum interconnection layer. Consequently, via-hole resistance in connection hole 6 is increased and/or an open failure is caused. As a result a problem arises that reliability in the connecting hole is reduced.
Another problem resulting from an increase in the aspect ratio of connection hole 6 is that coverage ratio in the connection hole of second aluminum interconnection layer 7 by the sputter method significantly decreases. When the coverage ratio of aluminum in the connection hole is low, not only reliability in connection hole 6 such as resistance against electro-migration is reduced but also a via-hole resistance increases.
This problem will be more serious for the connecting hole in a future semiconductor integrated circuit device with a larger aspect ratio (B/A) miniaturized in an order of sub-micron or an order of half-micron.